AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, ...

TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The ...

Pierre C. Fazan, Innovative Silicon Solutions, Le Landeron, Switzerland, Serguei Okhonin, Mikhail Nagoga, Jean-Michel Sallese, Swiss Federal Institute of Technology, Innovative Silicon Solutions, Le ...

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...

Data refresh and cell-layout issues must be addressed to optimally implement this space-saving alternative to SRAM technology. As the system-on-a-chip (SoC) era marches forward, there's a pressing ...

Engineers can now turbocharge their designs without having to sacrifice DRAM's high bit density to run at near-SRAM speeds. For applications where performance is of primary importance, designers have ...

iCometrue received enthusiastic responses following its show at SEMICON TAIWAN 2023. Some companies have expressed great interest in iCometrue's Logic Drive and Field Programmable Multi-Chip Package ...