When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...

Back gating, body bias, substrate bias, and back bias all refer to a technique for dynamically adjusting the threshold voltage of a CMOS transistor. CMOS transistors are often thought of as ...

(PhysOrg.com) -- While electronic devices have greatly improved in many regards, such as in storage capacity, graphics, and overall performance, etc., they still have a weight hanging around their ...

Designers rely on the accuracy of Process Design Kits (PDK¡¦s) for their IC designs. This paper describes independent verification of the PDK accuracy using a low-cost Die Level Process Monitor (DLPM) ...

SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice ...

Leakage in IC designs constitutes a significant amount of power dissipation because CMOS gates are not ideal switches. The leakage in CMOS gates varies significantly for different combinations of ...