Designed an 8-Kbit SRAM using sleep transistors to reduce power dissipation. 130nm technology is used to design SRAM cells and HSPICE simulations are used to determine the optimal number and sizes of ...
As AI, automotive, and data centers continue to scale exponentially, one part of the chip has quietly become a bottleneck: embedded memory. Modern designs now dedicate more than half of their silicon ...
MS in Electrical & Computer Engg. Seeking entry level positions in the digital hardware sector, i.e. FPGA emulation, VLSI/ASIC Design, Logic Design, Digital Systems & Embedded Systems.
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