EDN

Compiling FPGA netlists for formal verification

Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Semiconductor Engineering

Functional Design and Verification

Design is considered to be the creation of this RTL description, which feeds a logic synthesis flow. Logic synthesis forms the bridge into the implementation flow, which deals with issues such as the ...
Design-Reuse

Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often

Because today’s System-On-Chip (SOC) designs contain millions of transistors, design engineers must treat power dissipation as an important design goal for IP blocks and not as just a data-sheet ...
EDN

Estimate power at RTL to identify problems early

SoC power consumption is a key differentiating feature. The initial estimated power of the design is often less than the power use seen on silicon. This happens because there is no power estimation ...
Semiconductor Engineering

Calypto Design Systems, Inc.

Calypto focuses on development tools that are generally at higher levels of abstraction than RTL. The company was originally know as a pioneer in the sequential logic equivalence checking (SLEC) field ...