EDN

Best Practices for a Reusable Verification Environment

Verification reuse is critical to the productivity and efficiency of system-on-chip (SoC) verification. The foundation of this technique is well-designed verification codes and components that ...
Electronic Design

SoC Verification Environment Allows Configurable HDL Checks

A new version of the Verification Navigator Integrated Design Verification Environment features significant enhancements to the VN-Check Configurable HDL Checker, the ...
EDN

TransEDA enhances verification environment

SAN MATEO, Calif. — TransEDA plc has added the VN-Control application-specific test-automation tool and upgraded two other tools in the latest revision of its Verification Navigator integrated ...
Semiconductor Engineering

Merging Verification And Test

While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with ...
Electronic Design

Twin DFT and Mission-Critical Safety Apps for Pre-Silicon Design Verification

Combining these Apps with an emulation environment makes it possible to increase fault coverage, increase production yield, and reduce ATE test time and cost. The design-for-test (DFT) technology was ...
Semiconductor Engineering

Preparing For Test Early In The Design Flow

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...