Applications demanding higher system bandwidth and lower power, such as converged notebooks, desktop PCs, and servers, continue to drive the evolution of industry standards, including DDR3 ...

Fig 1. In complex customer design applications, the memory, the I/O, the processor core voltage, and the FPGA power rails must be precisely sequenced and the slew rate must be controlled with tight ...

DDR3 extended DDR2’s On-Die Termination design by adding additional flexibility to optimise termination values for different conditions by acting as a way to manage the termination power consumption.

TI unveils next-generation 3-A DDR termination regulatorLinear regulator supports DDR3 power requirements for low-power-mode memory termination DALLAS (Aug. 4, 2008) – Texas Instruments Incorporated ...

The power struggle between DDR2 and DDR3 continues the tradeoff game between bandwidth and latency. The timing shifts required by the DDR3 flyby topology change the time at which byte lanes demand ...