EDN

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
EDN

DDR PHY interface spec to be released at Denali’s MemCon

SAN FRANCISCO — A DDR PHY Interface (DFI) specification, seeking to define a common interface between memory controller logic and the PHY interface, is set to be unveiled next week at an event hosted ...
Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...
Electronic Design

Test and Analysis GUI Targets DDR PHYs

This article appeared in Microwaves & RF and has been published here with permission. Check out our DAC 2023 coverage. At DAC 2023, OPENEDGES Technology will be in Booth 1354 demonstrating a beta ...
Semiconductor Engineering

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit? Physics ...
Semiconductor Engineering

Advantages Of LPDDR5: A New Clocking Scheme

Innovative new clocking schemes in the latest LPDDR standard enable easier implementation of controllers and PHYs at maximum data rate as well as new options for power consumption. Earlier this year, ...