CMOS power consumption can be halved by reducing threshold voltage variation, claims Californian firm SuVolta. Fujitsu has licensed the technology. “The PowerShrink platform consists of deeply ...

Voltage level shifters are pivotal components in modern CMOS integrated circuits, facilitating robust interfacing between domains operating at disparate voltage levels. Recent advancements in this ...

Back gating, body bias, substrate bias, and back bias all refer to a technique for dynamically adjusting the threshold voltage of a CMOS transistor. CMOS transistors are often thought of as ...

MUNICH, Gemany — Foundry services provider Austriamicrosystems extends its technology portfolio with a low threshold (LVT) CMOS process option based on its 0.35µm analog CMOS (C35) technology. The ...

Xicor has introduced a novel precision voltage reference which avoids laser trimming by incorporating a floating gate, and which consumes under 1?A in operation. The reference is based on a simple ...

SuVolta has revealed a bit more about their Deeply Depleted Channel (DDC) low power, CMOS transistor technology designed for embedded SoCs (System-on-chip). SuVolta's PowerShrink transistor (see DDC ...

Sunnyvale, Calif. — Advanced Linear Devices, Inc. announced an ultra-sensitive, high-performance electrically programmable analog device (EPAD) analog voltage comparator. Designated the ALD2321, the ...

Designers rely on the accuracy of Process Design Kits (PDK¡¦s) for their IC designs. This paper describes independent verification of the PDK accuracy using a low-cost Die Level Process Monitor (DLPM) ...

SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice ...