Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

The synchronous vs. asynchronous design debate erupts every now and then, usually when a vocal minority swears by asynchronous design, often claiming that asynchronous design delivers higher ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Moore’s Law has been the driving force behind computer evolution for more than five decades, fueling the relentless innovation that led to more transistors being added to increasingly smaller ...

Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low. Fig 2. When a CMOS input pin is at logic high or low ...