EDN

Using advanced logging techniques to debug & test SystemVerilog HDL code

SystemVerilog provides an advantage in addressing the verification complexity challenge—not simply as a new language for describing complex structures, but as a platform for driving a more efficient, ...
EDN

Delivering advanced SystemVerilog verification capabilities to design teams

Some might say you need to be a full-fledged verification expert or specialist with experience using the latest object-oriented languages to tap into the productivity benefits of advanced verification ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Sutherland HDL, Inc. "Sutherland HDL, a leader in advanced SystemVerilog training, has been pleased to use Questa in our training workshops, and to be an evaluator of Questa 6.2 and AVM. Questa ...
Design-Reuse

eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP

Integration of AMBA AHB AVM 3.0 Ensures Availability of OVM Compliant High-Quality Verification IP for Advanced SystemVerilog Verification Sunnyvale, CA., and Ahmedabad, India ­ -- June 13, 2008 ...
Design-Reuse

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

MOUNTAIN VIEW, Calif., July 26, 2006--Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion ...