EDN

Chip architecture allows “testless” design flow

As most ASIC designers are aware, there are two primary test-related issues that cause a high degree of pain and schedule delay in creating ASIC designs — the difficulty in adhering to DFT (Design For ...
Design-Reuse

Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms

Magma design flow supports ChipX CX5000 and future structured ASIC architectures SANTA CLARA, Calif., September 14, 2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design ...
Design-Reuse

Embedded Systems: Programmable Logic -> Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...